The disclosed embodiments relate to a delay-locked loop (DLL) and a semiconductor memory device including the same, and more particularly, to a method for achieving fast locking regardless of a duty error window, and a semiconductor memory device including the same.
With the increase of operating speed of semiconductor memory devices, devices for synchronizing signal timing are often used to efficiently transfer data between a semiconductor memory device and a memory controller. Examples of the devices are a phase-locked loop (PLL) and a DLL.
The PLL generates a voltage-controlled signal according to a phase difference between a received clock signal and a reproduction clock signal and changes the frequency of the reproduction clock signal in response to the voltage-controlled signal, thereby controlling the phase of the reproduction clock signal to follow the phase of the received clock signal. The DLL generates a voltage-controlled signal according to a phase difference between a received clock signal and a reproduction clock signal and changes the amount of delay for the reproduction clock signal in response to the voltage-controlled signal, thereby controlling the phase of the reproduction clock signal to follow the phase of the received clock signal.
The DLL is usually used in the field of digital signal processing or synchronous dynamic random access memory (SDRAM) devices. An example of a typical DLL including, among other things, a phase detector, a delay line, and delay control signals, can be seen in U.S. Pat. No. 7,184,509, which is incorporated herein by reference in its entirety. At the initial stage of operation, one type of DLL uses an inversion scheme to achieve fast locking. In the inversion scheme, whether to invert a reproduction clock signal is determined based on the phase difference between a received clock signal and the reproduction clock signal and then an inverted or non-inverted reproduction clock signal is output. When the phase difference between the received and the reproduction clock signals is at least one-half cycle, the non-inverted reproduction clock signal is output. When the phase difference is less than one-half cycle, the inverted reproduction clock signal is output. Accordingly, following time, i.e., delay time is shorter than one-half cycle. When a duty ratio of the reproduction clock signal changes, however, initial locking may be delayed.
FIGS. 1A through 1C are diagrams for explaining the inversion scheme used in the DLL. Referring to FIG. 1A, a phase difference τ1 between a received clock signal EXCLK and a reproduction clock signal RCLK is at least one-half cycle, i.e., τ1≧T/2. Thus, the DLL outputs a non-inverted reproduction clock signal, that is, the reproduction clock signal RCLK is synchronized with EXCLK as it is without being inverted.
Referring to FIG. 1B, a phase difference τ2 between the received clock signal EXCLK and the reproduction clock signal RCLK is less than one-half cycle, i.e., τ2<T/2. Therefore, the DLL produces an inverted reproduction clock signal RCLKB, that is, the reproduction clock signal RCLK is inverted and then synchronized with EXCLK.
Referring to FIG. 1C, in some situations, a reproduction clock signal ERCLK may have a duty ratio of greater or less than 50% (e.g., 40%, 45%, 55%, 60%). In some instances, if the phase of the ERCLK signal for locking purposes is determined based on the rising edge of the signal, a typical inversion fast locking DLL might cause the delay associated with locking to be longer than had the inversion fast locking DLL not been used. For example, as shown in FIG. 1C, a situation may occur where a rising edge of ERCLK occurs in the first half of the EXCLK cycle, such that the DLL inverts the ERCLK signal (as shown by ERCLKB) and uses that signal for locking. However, as shown in FIG. 1C, the delay associated with locking in that case (shown by arrow “1”) is actually longer than the delay that would have occurred for locking had the ERCLK signal not been inverted (shown by arrow “2”). Accordingly, initial locking is delayed more than is necessary, thereby decreasing operating speed.
To overcome this problem, a method of using a duty error window for a duty error in a received clock signal when determining whether to perform inversion has been introduced. However, the method is still inconvenient because the width of the duty error window needs to be changed according to the frequency of the received clock signal.